Real-time correlator

ABSTRACT

In various circumstances, such as the recovery of a signal from a noisy background, two signals x(t) and y(t) are to be correlated. In this invention x(t) is sampled at recurrence period n/fo (n is at least 2). The samples are put into a recirculating memory of circulation time (n+1)fo with erasure of existing samples at point of insertion. The memory is coupled to a multiplier which multiplies the output of the memory with synchronized samples of y(t). The output of the multiplier is applied to an averaging memory. Only one multiplier is used to give the correlation function at n different time delays and hence greatly simplified apparatus is provided.

United States Patent Wold [54] REAL-TIME CORRELATOR [72] Inventor: IvarWold, Farnborough, Hampshire, En-

gland [73] Assignee: The Solartron Electronic Group Limited,

Famborough, England 22 Filed: May 27,1970

21 Appl.No.: 40,987

[30] Foreign Application Priority Data May 28, 1969 Great Britain..27,044/69 [52] US. Cl. ..235/l8l,343/l00 CL [51] Int. Cl. ..G06f15/34, G06f 7/04 [58] Field of Search ..235/1 8 l 343/100 CL [56]References Cited OTHER PUBLICATIONS Gatland, H. B. et al., A CorrelationFunction Computer Feb. 29, 1972 Using Delta Modulation Techniques," ln.1. Sci. lnstrum. 42(8): p. 529-532. Aug. 1965. Q 184.17.

Primary ExaminerMalcolm A. Morrison Assistant Examiner-R. StephenDildine, Jr. Attorney-William R. Sherman, Stewart F. Moore, Jerry M.Presson and Roylance, Abrams, Kruger, Berdo and Kaul [5 7] ABSTRACT Invarious circumstances, such as the recovery of a signal from a noisybackground, two signals x(t) and y(t) are to be correlated. In thisinvention x(t) is sampled at recurrence period n/f (n is at least 2).The samples are put into a recirculating memory of circulation time (n+1)f, with erasure of existing samples at point of insertion. The memoryis coupled to a multiplier which multiplies the output of the memorywith synchronized samples of y(t). The output of the multiplier isapplied to an averaging memory. Only one multiplier is used to give thecorrelation function at n different time delays and hence greatlysimplified apparatus is provided.

5 Claims, 6 Drawing Figures CLOCK 12 W TIME COMPRESSED OUTPUTPATENTEUFEB29 m2 SHEET 2 [IF 5 kmhwswk NED PAIENTEDFms 1972 SHEET l- UF5 PATENTEUFEB 2 9 I972 SHEET 5 OF 5 SWITCH DRIVER SIGN REAL-TIMECORRELATOR The present invention relates to real-time correlators.

Real-time correlators have various applications such as the recovery ofsignals in a transmission system especially where there is significantbackground noise, or flow measurement in pipes, or speed measurement offor example strip in a strip mill.

Derivation or measurement of correlation functions are relatively easyon a point-to-point basis, but real-time computation of correlationfunctions has required a large number of parallel computing circuits.For example arrangements are described in the Princeton Applied ResearchCorporation Technical Bulletin No. 149 and Electronics, Oct. 31, 1966which makes use of parallel output shift registers 100 elements long and100 hybrid multipliers to compute real-time correlation functions.

An object of the present invention is to provide an improved real-timecorrelator of substantially simplified construction.

According to the present invention a real-time correlator comprises afirst signal sampler for sampling a first signal x(t) of two signalsx(r) and y(t) to be correlated and arranged to provide samples of x(t)at a recurrence period of n/f, where n is an integer of at least 2 andf, is a given frequency, a recirculating memory having a circulatingtime of (n+l)/f means coupling the first sampler to the memory andarranged to inject each sample of .t(t) as it occurs into the memorywith erasure of any previous sample occupying the position in the memoryat which the injected sample is received, means coupling the memory to amultiplier to apply to the multiplier the sequence of samplescirculating in the memory, a second sampler for sampling the secondsignal y(t) and arranged to provide samples thereof at the saidrecurrence period of n/f and to apply each sample of the second signaly(t) for an interval of n/f to the multiplier, and means for applyingthe output of the multiplier to an averaging memory providing an outputrepresentative of the correlation function of x(t) and y(t) for ndifferent time delays at increments of llf Thus by means of theinvention a real-time correlator can be provided with only onemultiplier and giving the correlation function at n different timedelays.

The invention will now be described by way of example with reference tothe accompanying drawings, in which FIG. I is a block diagram of a knowntime-compressor,

FIG. 2 is an explanatory diagram used in describing the operation of theapparatus shown in FIG. 1,

FIG. 3 is a block diagram of one embodiment of the inventron,

FIG. 4 is an explanatory diagram for use in conjunction with FIG. 3.

FIG. 5 is a block diagram of an averaging memory used in the embodimentof FIG. 3, and

FIG. 6 herewith is a circuit diagram of a hybrid multiplier.

Referring to FIG. 1, the time-compressor shown can be as used in theFederal Scientific Corporation Spectrum Analyser Model UA7 and describedin Federal Scientific Corporation Technical Bulletin 662 July 1966. Aninput terminal 10 is connected to a sampler and analogue-to-digital(A/D) converter 11. The signal x(r) applied to the terminal 10 can be ofany analogue form. Sample-command signals are applied to the sampler andA/D converter 11 from a clock-pulse generator 12 of frequency f througha frequency divider 13 of division ratio n.

Another output from the clock-pulse generator 12 is applied directly toa shift register 14 to provide shift-command pulses therefor and theoutput of the A/D converter 11 is applied to the shift register 14through a selector switch 15. The switch 15 is an electronic switch butfor simplicity in the drawing it is shown schematically as a mechanicalswitch.

The shift-register 14 is arranged as a recirculating memory by acoupling 16 from the last stage thereof to the first stage through theswitch 15. A bistable circuit 17 controls the switch 15 which isnormally in its reset condition whereby the coupling 16 is connected tothe first stage of the shift register which then functions as therecirculating memory.

The bistable circuit 17 is reset by clock-pulses applied directlythereto from the clock-pulse generator 12 and is set by eachsample-command pulse which is also applied thereto from the divider 13.

When set by a command pulse the bistable circuit 17 causes the switch 15to disconnect the coupling 16 from the first stage of the shift registerand to connect the output of the A/D converter in its place. An outputterminal 18 is connected to the output side of the switch 15.

Given that the clock-pulse frequency is f,, and the divider l3 dividesby n, the shift register is arranged to have (n+1 stages.

In operation, the shift register recirculating memory 14 receivesshift-command pulses at the frequency f,, whereas the sampler and A/Dconverter 11 receives one sample-command pulse for every n clock-pulses.The bistable circuit 17 is also set by each sample-command pulse andhence is set once for every n clock-pulses.

Simultaneous operation of the switch 15 and the sampler and A/Dconverter 11 by the sample-command pulse causes the digitised sample ofthe signal at 10 to be put into the first stage of the memory 14. Thesample is shifted around the memory at the frequency f,, and whenshifted into the last stage the n' clock-pulse and hence the nextsample-command pulse occurs. Thus the second digitised sample is putinto the first stage of the memory.

When the next shift-command pulse occurs the second sample is shiftedinto the second stage and the first sample into the first stage. Thusthe two samples move through the memory in juxtaposition.

This action continues until samples occupy all stages of the register.On the occurrence of the next sample-command pulse transfer of thesample in the last into the first stage is prevented by operation of theswitch 15 whereby that sample is erased and a new sample takes itsplace. This erasure and injection of a new sample takes place with everysucceeding sample-command pulse.

Referring now to FIG. 2, this is an explanatory diagram illustrating theaction of the arrangement of FIG. 1 for the simple case of n=3 and hencethe shift register has four stages. In FIG. 2 seventeen shift-commandperiods are marked 1 to 17 above corresponding columns each of foursquares. The four squares proceeding from the bottom to the top in eachcolumn represent the four stages of the shift register in order fromfirst to last. The samples are given the reference x x .x and theposition of each sample in the register for each shift-command period isas shown. The arrows 19 indicate sample-command pulses causing newsamples to be injected into the register. The arrow 20 indicates thedirection in which samples are shifted through the register.

Thus the first sample is injected in period 1 and is shifted in periods2 and 3 to the second and third stages respectively of the register. Onthe occurrence of the next sample-command pulse (period 4) x, is shiftedinto the fourth stage and x is injected into the first stage. In period5 x, is recirculated into the first stage and x is shifted into thesecond stage and so on.

In period 10 the register is filled and contains samples x x,, x and 1:as shown. AS shown in period 13 when x, is injected x is erased.Similarly in period 16 when x is injected x is erased.

By taking an output from the first stage of the register the output fromperiod 7 onwards consists of x x x x.,, x x x x.,, x x x occurring atthe frequency f, from samples taken at the frequency f,,/3.

Referring now to FIG. 3, this is a block diagram of a realtimecorrelator according to the invention embodying the apparatus of FIG. 1.Like parts in FIGS. 1 and 3 are given the same reference.

The function of the arrangement of FIG. 3 is to correlate a signal y(t)applied to an input terminal 21 with a signal x(t) applied to the inputterminal 10.

Sample-command pulses from the divider 13 are applied to a sampler 22 inaddition to the sampler and AID converter 11. The sampler 22 is arrangedto sample the signal y(t) on the occurrence of each sample-commandsignal and to deliver the sampled value to its output until theoccurrence of the next sample-command pulse.

FIG. 4 shows the output at 18 and the output at 23 from the sampler 22for the case where n=3 as described with reference to FIG. 1. It will beappreciated that FIG. 4 consists of FIG. 2

with the addition of the signalx(t), the signal y(t) and the samples yto y of y(t) the samples y, to y being indicated in thick lines such as24.

The digital output at 18 and the analogue output at 23 are applied to ahybrid multiplier 25 which is a known device but will be describedlater. In the multiplier they are multiplied together and the product inanalogue form appears at 26 from where it is applied to the inputterminal 27 of an averaging memory. Clock-pulses from the generator 12are also applied to the averaging memory 28 through an input terminal29, and reset pluses at the sample-command frequency are applied to theaveraging memory 28 from the divider 13 through a terminal 30.

The averaging memory is a known arrangement and may be as described inPrinceton Applied Research Corporation Technical Bulletin T162. However,a brief description will now be given with reference to FIG. 5. Theinput terminal 27 is connected through an amplifier A and a resistorR(t) to a rail 1. Between the rail J and earth is an array of capacitorsC C C each with a series connected switch S S S The switches arecontrolled by a sequential scanner S in such a way that they are closedfor a short period in turn by clock-pulses applied at 29, only oneswitch being closed at any one time. Each cycle or scan is made torepeat by a reset pulse applied at 30.

The rail .l is connected to the input of an amplifier A which isarranged to have a very high input impedance. Thus with any one of theswitches closed, say switch 5,, the output from the amplifier A is thevoltage stored on the capacitor C,- which approaches the value of theinput signal at 27 in the interval when S,- is closed.

It will be appreciated therefore that in each scanning cycle thevoltages on the capacitors are modified to a new estimate of averagewhich appears at the same time at the output terminal V, of theamplifier A The sequential scanner S is arranged to provide an output atV, proportional to memory position, i.e., with switch S, closed theoutput voltage is V, where V is a constant voltage. Thus the output at Vcan be displayed on a cathode ray tube using V for horizontal deflectionand V for vertical deflection.

In FIG. 3 the averaging memory of FIG. 5 is provided with n stages andit will be appreciated that following the beginning of each cycle the rproduct from the multiplier is always put into the r" position in theaveraging memory.

The output from the hybrid multiplier will be as follows for the case ofn=3:

Thus the voltage on, say, C, in the averaging memory will approach thecorrelation between x(r) and y(t) at a delay of 'r,F=r/f, seconds. Anoscilloscope connected to display the output V against V, will show thecorrelation function of x(t) and y(t) for 14 different time delays atincrements of l /f,,.

In the known averaging memory shown in FIG. 5 the resistor R(t) is fixedin value. We have found that true timeaveraging can be obtained byarranging that R(t) is increased before or after each scanning cyclesuch that the averaging RC time constant is approximately equal to thetime which has elapsed since the start of the measurement. This can bearranged by means of a suitable network or array of resistors which areswitch through appropriate switches controlled by a counter which isincremented after each scan.

Referring to FIG. 6, this is a circuit diagram of a hybrid multipljer.The analo ue input Y is a plied at the input 23 and the digital input XIS mary and app red in parallel at 18 together with a sign-bitindicating+ or applied at 18'.

The Y-input is applied directly to one input of a selector switch 31 andthrough an inverting amplifier 32 of unity gain to the second input ofthe selector switch 31. The X-input includes the sign-bit applied at 18'and this operates to control the switch 31 through a switch-drivercircuit 33 which merely provides adequate power for operating theswitches shown. When the sign of X is negative the sign-bit causes theselector switch 31 to select the input through the amplifier 32. Whenthe sign-bit is positive it causes the selector switch 31 to select thedirect Y-input from 23.

The output of the switch 31 is connected through switches 34, 35, 36 and37 in series with conductances 38, 39, 40 and 41 respectively to theinput of an operational amplifier 42 with feedback conductance 43.

The conductances 38-41 are binary weighted, i.e., have values in theratios 1, 2, 4 and 8 for the 4-bit arrangement shown. With thisarrangement the gain of the operational amplifier is gJg; where g, istotal input conductance determined by which of the switch 34 to 37 areclosed and g; is the conductance of 43.

The operation of the switches 34 to 37 is governed by the binary digitsof the X-signal and hence the analogue output at 26 is dependent uponthe product of the binary X-signal and the analogue Y-signal.

The switches shown as mechanical switches in FIG. 6 can of course be inelectronic form.

What is claimed is:

l. A real-time correlator, comprising first and second inputs to receivefirst and second signals x(t) and y(t) to be correlated, a firstsignal-sampler connected to said first input to provide samples of x(t)at a recurrence period of n/f where n is an integer of at least 2 and fis a given frequency, a recirculating memory having a circulating timeof (n+1 )lf means coupling said first sampler to said recirculatingmemory to inject each sample of x(t) as it occurs into saidrecirculating memory with erasure of any previous sample occupying theposition in the recirculating memory at which the injected sample isreceived, means coupling the recirculating memory to a multiplier toapply thereto the sequence of samples circulating in said memory, asecond signal-sampler connected to said second input to provide samplesof y(l) at said recurrence period rr/f each for an interval of n/f meansto apply said samples of y(r) to said multiplier, an averaging memory ofn stages driven at a clock-frequency f and means for applying the outputof said multiplier to said averaging memory to provide an outputrepresentative of the correlation function of x(t) and y(t) for ndifferent time delays at increments of I I1}.

2.. A real-time correlator as claimed in claim 1, wherein saidrecirculating memory is a digital shift register with a feedback pathfrom output to input.

3. A real-time correlator as claimed in claim 2, and comprising ananalogue-to-digital converter connected between said first sampler andsaid recirculating memory.

4. A real-time correlator as claimed in claim 3, wherein the multiplieris a hybrid multiplier-to-receiver digital input from said recirculatingmemory and analogue input from said second sampler.

5. A real-time correlator according to claim 1, wherein said meanscoupling said first sampler to said recirculating memory comprise meansto break a recirculating path of said recirculating memory to erase asignal therein and means to inject a sample in place of said erasedsignal.

1. A real-time correlator, comprising first and second inputs to receivefirst and second signals x(t) and y(t) to be correlated, a firstsignal-sampler connected to said first input to provide samples of x(t)at a recurrence period of n/fo where n is an integer of at least 2 andfo is a given frequency, a recirculating memory having a circulatingtime of (n+1)/fo, means coupling said first sampler to saidrecirculating memory to inject each sample of x(t) as it occurs intosaid recirculating memory with erasure of any previous sample occupyingthe position in the recirculating memory at which the injected sample isreceived, means coupling the recirculating memory to a multiplier toapply thereto the sequence of samples circulating in said memory, asecond signal-sampler connected to said second input to provide samplesof y(t) at said recurrence period n/fo each for an interval of n/fo,means to apply said samples of y(t) to said multiplier, an averagingmemory of n stages driven at a clockfrequency fo, and means for applyingthe output of said multiplier to said averaging memory to provide anoutput representative of the correlation function of x(t) and y(t) for ndifferent time delays at increments of 1/fo.
 2. A real-time correlatoras claimed in claim 1, wherein said recirculating memory is a digitalshift register with a feedback path from output to input.
 3. A real-timecorrelator as claimed in claim 2, and comprising an analogue-to-digitalconverter connected between said first sampler and said recirculatingmemory.
 4. A real-time correlator as claimed in claim 3, wherein themultiplier is a hybrid multiplier-to-receiver digital input from saidrecirculating memory and analogue input from said second sampler.
 5. Areal-time correlator according to claim 1, wherein said means couplingsaid first sampler to said recirculating memory comprise means to breaka recirculating path of said recirculating memory to erase a signaltherein and means to inject a sample in place of said erased signal.